SAD implementation in FPGA hardware
نویسندگان
چکیده
In this paper, we propose a new unit intended to augment a general-purpose core that is able to perform a SAD operation. We show that the SAD implementation can easily be extended to perform the complete SAD operation. The SAD operation is commonly used in many multimedia standards, including MPEG-1 and MPEG-2. We have chosen to implement the SAD operation in field-programmable gate arrays (FPGAs), because it provides increased flexibility, good-enough performance, and faster design times. We performed simulations to validate the functionality of the SAD implementation using the MAX+plus II (version 9.23 BASELINE) software from Altera and synthesis using the FPGA Express (version 3.5) software from Synopsis. When our SAD unit was synthesized by targeting the FLEX20KE family of Altera, we obtained the following results for area and clock frequency: 1699 LUTs and 197 MHz, respectively. Keywords— Sum of absolute differences, motion estimation, video coding, field programmable gate arrays.
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